1. Field of the Invention
The present invention relates to an improved cache control system to reduce the amount of loading of the CPU driven control signals.
2. Description of the Related Art
In the electronics industry, there is an ever increasing demand for increased performance from computer systems. This need also includes a need for increased system memory capacities. More specifically, there exists a constant need for adding additional cache storage capacity to decrease the system's performance time for memory accesses. Currently, computer system designers are looking toward 50 MHz systems coupled with up to 512 Kb of external cache storage area.
The cache storage area responds directly to memory requests from a central processing unit (CPU) as well as from other subsystems, such as direct memory access (DMA) controllers, memory controllers, other cache controllers, I/O controllers and peripheral controllers. The CPU uses an address status output (ADS*) signal as an indicator to the other controllers in the system and to the cache storage area that the CPU is starting a bus cycle. (As used herein, an asterisk at the end of a signal name or mnemonic indicates a signal that is active at a low logic level.) The ADS* signal indicates that the address and bus definition signals from the CPU are valid and have been presented to the system bus. The cache control and bus control circuitry must sample the bus cycle definition signals from the CPU on the next rising edge of the clock after the ADS* signal is driven active. In the desired 50 MHz system, the signals must be sampled within 20 ns, one clock period, from the receipt of the ADS* signal. In addition, the ADS, signal must be received to latch the valid address signals into each of the synchronous static random access memory chips, or synchronous SRAM chips, which make up the cache storage area before the required set up time of the synchronous SRAM. The set up time is the amount of time that the ADS* signal must be present at the input of the synchronous SRAM before the receipt of the next clock cycle which will clock the address signals into the synchronous SRAM. The set-up time for a typical synchronous SRAM is between 2-3 ns.
With the increased demands for larger banks of external cache, such as 256 Kb and 512 Kb banks of cache, the number of synchronous SRAM chips required to provide the larger banks of external cache is increasing, because the capacity of the individual synchronous SRAM chips has stayed the same. Using 32 Kb.times.9 bit synchronous SRAMs for the cache, a 256 Kb cache will require eight synchronous SRAM chips. Each of the synchronous SRAM chips must be individually driven by the ADS* signal to enable each chip to sense when the CPU is beginning a bus cycle. The connection of the ADS* signal to the bus control logic as well as to the eight synchronous SRAM chips causes the ADS* signal to become excessively loaded. This excessive loading of the ADS* signal can cause delays in the receipt of the ADS* signal by the synchronous SRAM chips, particularly those SRAM chips which are located farthest away from the CPU and are thus subject to the longest propagation delays in receipt of the ADS* signal. Current CPU's such as the INTEL 486DX provide an ADS* signal which is a 12 ns signal when the signal is unloaded. By loading down the ADS* signal with eight synchronous SRAMs along with its other control responsibilities in the system, the delay in the receipt of the ADS* signal can be increased from 12 ns when the ADS* signal is unloaded to up to 18 ns when the signal is loaded by the cache and the other control circuits. Typically, a 4-6 ns delay in the receipt of the ADS* signal by the individual chips is expected depending on the location of the chips and the number of chips which are tied to the ADS* signal. This 4-6 ns delay in the receipt of the ADS* signal may be unacceptable for some synchronous SRAMs. For example, if the CPU is running on a 20 ns clock, i.e., a 50 MHz system, and the delay in the receipt of the ADS* signal is increased from 12 ns to 18 ns, the ADS* signal would arrive 2 ns before the next clock signal and would not meet the required minimum 3 ns set up time of most synchronous SRAMs.
Further, the ADS* signal is connected to other logic circuits which have longer required set up times, up to 5 ns in some cases. By over loading the ADS* signal with all of the synchronous SRAMs, the ADS* signal will not meet the set up times required by the most of the system control logic that the ADS* signal is connected to and the system will not be able to function properly.
As disclosed in the prior art, to prevent the excessive loading of the ADS* signal, the ADS* signal can be buffered. However, buffering the ADS* signal results in an inherent increased delay in the receipt of the signal caused by propagation delay within the buffer circuits. The fastest buffers available would still result in a 4-5 ns delay in the receipt of the ADS* signal. This 4-5 ns delay caused by buffering is essentially the same scale of delay that is caused by the excessive loading of the ADS* signal. For example, if the CPU is running on a 20 ns clock, i.e., a 50 MHz system, and the delay in the receipt of the ADS* signal is increased due to the buffering from 12 ns to 17 ns, the ADS* signal would arrive at best 3 ns before the next clock signal and may not always meet the required minimum 3 ns set up time of most synchronous SRAMs. Further, the 3 ns arrival of the ADS* signal before the next clock signal would not be acceptable for the other logic circuits which require set up times in the order of 5 ns.
Therefore there exists a need in the prior art to enable the unloading of the bus control signals which are driven by the CPU in order to improve the system performance times for memory accesses while still enabling an increase in the system memory capacity.